1. Field of the Invention
This invention relates to a semiconductor device using a standard cell system, and more particularly to a semiconductor device having improved inter-cell wiring for connecting standard cells to one another.
2. Description of the Related Art
A standard cell type semiconductor device is known as one type of semiconductor device (ASIC) for a special application. The standard cell is a standard logic circuit such as an AND, NAND, OR or NOR. In the standard cell system, the standard cells are registered in a library, and various circuits can be designed by variously combining the standard cells in the most suitable cell arrangement pattern and in the most suitable inter-cell wiring pattern. For this reason, the standard cell system is mainly used for semiconductor devices which will be manufactured each time small orders have been received.
The wirings inside the standard cell or between the standard cells are formed of a conductive layer having three layers sequentially laminated on the main surface of a semiconductor substrate.
More specifically, a polysilicon layer, first and second aluminum layers are sequentially formed from the main surface of the semiconductor substrate. The polysilicon layer is used for the gate electrodes of transistors or the like, the first aluminum layer is used for forming wirings connecting the gate electrodes of the transistors to one another and intra-cell wirings such as power source lines or the like arranged in a row direction of the standard cell, and a second aluminum layer is used for wirings for connection between the cells or inter-cell wirings arranged in a direction perpendicular to the power source lines.
In the standard cell system, the inter-cell wiring pattern or the pattern of the wirings in the cell formed of the first aluminum layer is standardized and registered. In the registered standard cell, two power source lines of high and low potentials which are necessary for circuit operation are of the first aluminum layer and are separately arranged in parallel with each other at the end portion of the standard cell area. Further, since the arranged positions of the two power source lines are set on the end portion of the standard cell, the power source lines can be arranged in the same position in all of the registered standard cells.
In the semiconductor device using the standard cell system, a plurality of standard cells as described above are arranged in a direction along the power source lines. The thus arranged standard cells are called a standard cell array. Further, in the present device, a plurality of standard cell arrays are on the semiconductor substrate.
The wirings of the second aluminum layer are connected to the intra-cell wirings of the first aluminum layer, and as described above, arranged in a direction perpendicular to the power source lines to constitute part of the inter-cell wirings. The inter-cell wirings of the second aluminum layer to extend over the power source lines to an area other than the standard cell area, particularly, between the standard cell array. The inter-cell wirings for connection between the standard cells or between the inter-cell wirings formed of the second aluminum layer are of the first aluminum layer, and arranged in a direction perpendicular to the inter-cell wirings formed of the second aluminum layer between the standard cell arrays. The inter-cell wirings of the first aluminum layer and the inter-cell wirings formed of the second aluminum layer are connected to each other between the standard cell arrays so as to attain a desired circuit output.
An area between the standard cell arrays is determined as a wiring area for electrically connecting the standard cells to one another to attain a desired circuit output and is generally called a channel region.
However, in the conventional device in which the channel region is provided between the standard cell arrays, the area of the channel region on the semiconductor substrate is further increased with an increase in the number of inter-cell wirings necessary for attaining more complicated logic functions.
As a result, the integration density of the semiconductor device formed by using the standard cell system cannot be easily enhanced.